This invention relates generally to current limiting circuitry and, more particularly, to circuitry for limiting the output current of a power substrate PNP transistor.
In most cases where it is necessary to provide means for limiting short circuit current, a resistor is placed in series with the power path (i.e. in series with the circuit's output), and the voltage across the resistor is monitored and compared with a reference voltage. This traditional approach, however, becomes extremely complicated in the case of a vertical substrate PNP device since the substrate or output voltage may swing over a wide range thus requiring that the current sensing circuitry have a very wide dynamic range.
An alternative approach is to sense the current flowing in the emitters of the power device by placing the resistor in series with the the total current. Unfortunately, if a low input-to-output voltage device is desired (i.e. approximately zero volts from the emitter to the collector when the device saturates), current flowing through the resistors in series with the emitters will result in a voltage drop, and the ability to achieve a low input-to-output voltage device will be lost.